I have been hard at work creating an implementation of the Intel 8080 processor in discrete TTL components, and this is what I have come up with:
In theory, it should be able to emulate most of the opcodes that the 8080 can, with a few exceptions such as lack of binary coded decimal support (which seems pointless for the extra effort it would need) and the lack of a parity check. It also does not currently have the ability to service interrupts, but that is planned to be added later once major functionality is tested. I have run into one problem though, as I had originally planned to use a single phase clock and have all processor function happen when the uCode ROMs propagate, but I have now run into a wall where I can not implement it very simply without major problems with race conditions being likely. So, I am going to make a small redesign to the processor to have it run on two clock phases: Phase 1 will advance the uSequencer and activate outputs, and Phase 2 will clock the registers.