The first version of the processor, which I have named KIRV, will be a microprogrammed RV32I implementation. This version will focus on being reliable and simple so as to serve as a reference for the more complicated designs later. It will be the first version to be able to be synthesized on an FPGA and should be compact enough to fit on most FPGA boards.
The basic layout of this project is based on a previous 16 bit processor I implemented in Verilog, I will likely make a post about that one later. That processor had a very similar datapath, so the main differences will be how the program counter is handled on branch instructions and the datapath width.
Here is the simple datapath for the microprogrammed version:
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